A flash memory device is a kind of programmable read only memory (PROM) capable of writing, erasing, and reading information.
Flash memory devices can be classified as NOR type and NAND type, according to their cell array structure. NOR type flash memory devices have cells disposed in parallel between a bit line and a ground, and NAND type flash memory devices have cells disposed in series between a bit line and a ground.
The NOR type flash memory device enables high-speed random access when performing reading operations, so it is typically used for booting mobile phones. The NAND type flash memory device has a slow reading speed and a rapid writing speed, so it is suitable to store data and is favorable for miniaturization.
Flash memory devices can be further classified into stack gate type and split gate type, according to the structure of a unit cell. Flash memory devices can be classified even further as floating gate devices and silicon-oxide-nitride-oxide-silicon (SONOS) devices, according to the type of charge storage layer. A floating gate device typically includes a floating gate of polycrystal silicon surrounded by an insulator. Charges are often injected into or emitted from a floating gate by channel hot carrier injection or Fowler-Nordheim tunneling (F-N tunneling), so that data can be stored or erased.
FIG. 1 shows the layout of a cell array in a related art flash memory device.
Referring to FIG. 1, a plurality of word lines 1 and a plurality of bit lines 3 intersecting the word lines 1 are disposed on the device. Cell devices (not shown) are disposed at the intersections of the word lines 1 and the bit lines 3. Contact plugs 5, which are electrically connected to the bit lines 3, are disposed between adjacent first and second cell devices. The adjacent first and second cell devices are electrically connected to one contact plug 5.
Corresponding cell devices are typically selected by the word lines 1, and data signals supplied to the bit lines 3 are generally stored in the selected cell devices through the contact plugs 5. Data signals stored in the selected cell devices can also be supplied to the bit lines 3 through the contact plugs 5.
FIG. 2 is a cross-sectional view taken along line I-I′ of the cell array of FIG. 1.
Referring to FIG. 2, a unit cell can be defined by the first and second cell devices 26 and 28.
In order to partition the cell devices on a semiconductor substrate 11, shallow trench isolations (STIs) 13 are formed.
The first and second cell devices 26 and 28 are disposed between the adjacent STIs 13.
A gate oxide layer 15, a floating gate 16, an oxide-nitride-oxide (ONO) layer 17, and a control gate 18 are sequentially formed on the semiconductor substrate 11.
In order to isolate and protect a gate region, spacers 21 are formed on sidewalls of the gate oxide layer 15, floating gate 16, ONO layer 17, and control gate 18. The spacers 21 may include a first tetraethyl orthosilicate (TEOS) layer 21a, a silicon nitride (SiN) layer 21b, and a second TEOS layer 21c. 
Source and drain regions 23 can be formed in the semiconductor substrate 11 adjacent to the spacers 21.
Thus, the first and second cell devices 26 and 28 can be defined by the source and drain regions 23, the spacers 21, and the gate region including the gate oxide layer 15, floating gate 16, ONO layer 17, and control gate 18.
In order to facilitate electrical contact with an external interconnection that may be present, silicide layers (not shown) can be formed on the control gate 18, as well as on the source and drain regions 23.
Before the silicide layers are formed, a cleaning process is typically performed on the control gate 18 and the source and drain regions 23 to remove any foreign materials from them that may be present.
However, when the cleaning process is performed, the first and second TEOS layers 21 a and 21c of each spacer 21 often react with a cleaning solution, and thus are removed in part.
Specifically, an undercut phenomenon, in which portions of the first TEOS layer 21a of each spacer 21 is removed, often occurs.
This undercut phenomenon may occur to a great depth, such that the undercut parts beginning near a top surface of the spacer 21 and a bottom side surface of the spacer 21 of the first TEOS layers 21a of the adjacent spacers 21 are connected to each other.
Accordingly, when the contact plugs are formed, a conductive material for the contact plugs can infiltrate into the undercut parts. As a result, the adjacent contact plugs can be electrically interconnected through the conductive material infiltrated into the undercut parts, leading to a bit failure caused by a defective bridge between the cell devices.
Thus, there exists a need in the art for an improved flash memory device and fabricating method thereof.